Those concerned with the development of integrated circuit technology have continually sought to develop structures and methods of fabrication which will increase circuit packing density, circuit performance, and improve process yields.
For example, some designers of submicron MOSFETs have employed a so-called lightly-doped drain structure (LDD). The LDD structure features a shallow junction near the device gate and a deeper junction spaced more remotely from the gate. The shallow junction helps to avoid punch-through and short channel effects. However, the shallow junction exhibits a high sheet resistance and therefore may, taken alone, adversely affect device performance.
Various approaches to LDD technology have been investigated in the past. Among them are: Pfiester, "LDD MOSFETs Using Disposable Side Wall Spacer Technology," IEEE Electron Device Letters V. 9(4), p. 189-192 (1988) and Oh et al., "Simultaneous Formation of Shallow-Deep Stepped Source/Drain for Submicron CMOS," VLSI Technology Symposium, p. 73-74 (1988).
Some of the above-mentioned publications feature the use of silicide processes in an attempt to reduce the high sheet resistance problems mentioned above. However, an examination of the published processes reveals various practical difficulties with their implementation.
Whether or not an LDD structure is employed, various other problems may occur during device processing which may subsequently degrade integrated circuit performance. For example, various steps associated with silicide processes may cause either damage to the silicon substrate surface or may contribute to shorting between the source/drain and gate.
Another problem confronting integrated circuit designers is the need to interconnect individual transistors with increasingly complex interconnection schemes. Designers frequently employ gate-level local interconnection schemes. However, if it is either necessary or desirable for a local interconnection line to cross over a gate runner, care must be taken to prevent electrical contact between the gate runner and the local interconnection line. Those concerned with the development of integrated circuits have consistently sought processes which will solve the above and other problems.